1. Field of the Invention
The present invention relates to a memory device formed using a semiconductor.
2. Description of the Related Art
Semiconductor memory devices include dynamic random access memories (DRAMs) (see Patent Document 1, for example). In a DRAM, memory cells 105 each including a cell transistor 106 and a capacitor 107 as illustrated in FIG. 2B are arranged in a matrix as illustrated in FIG. 2A, and a gate and a drain of the cell transistor 106 are connected to a word line 103 and a bit line 104, respectively. Moreover, the DRAM includes a row driver 101 for driving a plurality of word lines and a column driver 102 for driving a plurality of bit lines.
The DRAM is powered by an external power supply to drive the row driver 101 and the column driver 102. Note that a cell transistor formed using silicon semiconductor has a small drain current (off-state current) even in the off state, and thus requires tens of refresh operations (operations for replenishing the capacitor with charge) per second. In other words, the DRAM needs to be powered by the external power supply to retain a stored state.
In recent years, it has been found that charge can be retained for a very long period of time by utilizing the very low off-state current of transistors formed using an oxide semiconductor whose bandgap is two or more times that of silicon semiconductor. For example, the theoretical off-state current (drain current in the off state) of a semiconductor with a bandgap of 2.5 electron volts or more is 10−26 A or less. The use of a memory circuit utilizing this as a nonvolatile memory has been proposed (see Patent Documents 2 to 4).
A transistor used in such a memory needs to exhibit sufficiently high off resistance (the resistance of the transistor in the off state), i.e., sufficiently low off-state current. For example, in order to retain charge in a capacitor of 30 fF, which is the capacitance of capacitors used in a DRAM in common use, for 10 years, a transistor exhibiting a resistance of as high as 1×1022Ω or more in the off state is required. Assuming that the drain voltage is +1 V, the off-state current of the transistor needs to be 100 yA (1×10−22 A) or less.
The drain current of a transistor formed using an oxide semiconductor with a wide bandgap in the subthreshold region can be roughly estimated from the subthreshold value and the threshold voltage. The theoretical lower limit of the subthreshold value at room temperature (27° C.) is 60 mV/decade.
For example, assuming that the threshold voltage is +1 V, the subthreshold value is 60 mV/decade, and the drain current obtained when the threshold voltage is +1 V is 1 μA (the source potential Vs is 0 V, while the drain potential Vd is +1 V), the drain current is 100 yA with a gate potential Vg of +40 mV. With a gate potential Vg of 0 V, the drain current of the transistor is less than 100 yA, so that the charge in the capacitor can be retained for 10 years.
Note that the retention period is not limited to 10 years, and may be determined in the range from 10 seconds to 100 years depending on intended use. The capacitance of the capacitor or the off resistance or off-state current of the transistor may be set according to the retention period.
The above-described drain current is obtained at room temperature. In practice, some problems arise here. The subthreshold value depends on temperature. As temperature increases, the subthreshold value increases. Because it is also possible that the semiconductor memory device is stored at a high temperature, sufficient retention characteristics need to be also ensured at a temperature exceeding room temperature.
For example, the theoretical lower limit of the subthreshold value at 95° C. is 74 mV/decade. When the subthreshold value is 74 mV/decade, gate potential Vg with which the drain current becomes 100 yA is −180 mV. When the gate potential Vg is 0 V, the drain current is 10 zA (1×10−20 A), so that charge retention time is 1% of that at room temperature.
As transistor size is decreased, the subthreshold value increases owing to short channel effects. The conductivity type of silicon semiconductor can be controlled by doping. Therefore, in the case of an n-channel transistor, for example, short channel effects can be reduced by increasing the concentration of a p-type dopant in the channel formation region.
In contrast, the conductivity type of an oxide semiconductor cannot be controlled by controlling dopant concentration as in the case of silicon semiconductor. The intensity of one conductivity type of an oxide semiconductor can be changed, but the conductivity type of an oxide semiconductor cannot be reversed; for example, an n-type oxide semiconductor cannot be turned into a p-type one by doping. For this reason, short channel effects cannot be reduced by reversing the conductivity type of the channel formation region.
Therefore, with a channel length of 100 nm or less, the subthreshold value is 100 mV/decade or more, and the gate potential Vg needs to be maintained at −0.6 V or less. The threshold voltage is +1 V in the above description; when the threshold voltage is low, even the gate potential Vg at room temperature or with a long channel needs to be less than 0 V in order to sufficiently increase the off resistance. Note that the threshold voltage is dependent on the work function of a material for the gate; thus, it is difficult to increase the threshold voltage to +1.5 V or higher.
Under such conditions, data loss may occur when power from the external power supply to the semiconductor memory device is interrupted and the potential of the gate becomes the same as that of the source (i.e., Vg=0 V). Since potential is relative, the potentials of portions of the semiconductor memory device are assumed, in the description below, to become 0 V after the interruption of power from the external power supply, although it may take slightly longer or shorter.